library verilog;
use verilog.vl_types.all;
entity cmsdk_apb_watchdog_frc is
    port(
        PCLK            : in     vl_logic;
        PRESETn         : in     vl_logic;
        PENABLE         : in     vl_logic;
        PADDR           : in     vl_logic_vector(4 downto 2);
        PWRITE          : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        frc_sel         : in     vl_logic;
        wdog_lock       : in     vl_logic;
        WDOGCLK         : in     vl_logic;
        WDOGCLKEN       : in     vl_logic;
        WDOGRESn        : in     vl_logic;
        WDOGINT         : out    vl_logic;
        WDOGRES         : out    vl_logic;
        frc_data        : out    vl_logic_vector(31 downto 0)
    );
end cmsdk_apb_watchdog_frc;
